Generally in computer systems and especially in personal computer systems, data is transferred between various system devices such as a central processing unit (CPU), memory devices, and direct memory access (DMA) controllers. In addition, data is transferred between expansion elements such as input/output (I/O) devices, and between these I/O devices and the various system devices. The I/O devices and the system devices communicate with and amongst each other over computer buses, which comprise a series of conductors along which information is transmitted from any of several sources to any of several destinations. Many of the system devices and the I/O devices are capable of serving as bus controllers (i.e., devices which can control the computer system) and bus slaves (i.e., elements which are controlled by bus controllers).
Personal computer systems having more than one bus are known. Typically, a local bus is provided over which the CPU communicates with cache memory or a memory controller, and a system I/O bus is provided over which system bus devices such as the DMA controller, or the I/O devices, communicate with the system memory via the memory controller. The system I/O bus comprises a system bus and an I/O bus connected by a bus interface unit. The I/O devices communicate with one another over the I/O bus. The I/O devices are also typically required to communicate with system bus devices such as system memory. Such communications must travel over both the I/O bus and the system bus through the bus interface unit.
In some instances a device coupled to the I/O bus needs to either read from or write to an address location on another device which is also coupled to the I/O bus; and, in some instances a device coupled to the I/O bus needs to read from an address located in the system memory, which system memory is coupled to the local bus. In this type of system, the listing of the memory addresses is contained in the memory controller which is coupled to the system bus and a local bus CPU complex.
Thus, when a device coupled to the I/O bus needs to read from or write to a memory address, the signal would have to pass through the bus interface unit to the memory controller. Logic in the memory controller then determines whether the address is in system memory or in a device coupled to the I/O bus and then communicate this information to the device coupled to the I/O bus before it can start transferring information. However, this communication through the bus control unit requires that the control unit arbitrate for the system bus, then write the required address information to the memory controller. When the memory controller determines where the address is located, it must then have either delayed giving up of the system bus or if given up, must arbitrate to get the system bus back, and then write the address location back to the bus interface unit.
All of this arbitration and "handshaking" is time consuming and is inefficient, especially when the read or write involves a device coupled to the I/O bus address writing to or reading from an address in a device which is also coupled to the I/O bus. Indeed, in certain systems when a device coupled to the I/O bus needs to read or write to memory, an extra delay is programmed into the cycle to allow sufficient time to compare the address and write the locations to the required devices.
Accordingly, it is an object of this invention to provide an efficient determination of an address location which a device coupled to the I/O bus can write data to or read data from.